1. Field of the Invention
The field of the invention relates to semiconductor memory storage devices.
2. Description of the Prior Art
Semiconductor memory storage devices for storing data such as SRAM are known. There are ever increasing demands to reduce the power consumption, peak currents and area of these devices.
One key way of reducing the power consumption of such SRAM devices is to reduce the bit cell leakage by disabling the bit line precharge devices that are used to precharge the bit lines for a read or write. Disabling these devices essentially floats the bitlines and the bitline voltages will reach a steady state value which can be close to VSS the voltage level of the low power rail.
When returning from low power mode the bitlines must be precharged back to the full high power VDD level before beginning normal memory access operations. The precharge of all bitlines simultaneously for a large memory can lead to a very high peak current, which can collapse the power supply rail and potentially damage the silicon. If these peak currents are significantly higher than other currents that flow during normal operation then these currents will constrain the design of the memory that needs to take account of peak current requirements.
It is known to use active devices such as inverter chains to add a delay to a control signal for triggering this precharge in order to reduce the peak currents that occur if all of the bitlines of the memory are precharged together. The delay provided by these active devices varies with operating conditions. This means that in order to allow for different process corners and not generate peak currents beyond those allowed for in the design of the memory these delay devices are configured to provide a higher average delay than is generally required during normal operation in order to avoid failure at the process corners.
It would be desirable to provide a semiconductor memory with low power leakage and with reduced peak currents on return from low power mode.